It is desirable to minimize resistance and parasitic capacitance in the digit lines of memory arrays in semiconductor integrated circuits. Typically existing digit lines in memory arrays follow an up and down topography over the word lines for contact with the active areas of devices. This serpentine path increases the distance over which current must travel, thereby increasing the line resistance and the parasitic capacitance with surrounding layers. Futher, this curved topography creates problems of step coverage, conformality and definition of subsequently deposited layers on the wafer. In particular, the etch of a digit line that follows highly curved topography is somewhat difficult and creates a tendency for conductive poly stringers to form between adjacent digit lines causing a short. To avoid these stingers, a long overetch is needed. However, overetch results in notching of the digit line and thereby increases digit line resistance further.
It would be desirable to develop a method which reduces digit line resistance as well as these other problems.